US 11,683,611 B1
Resettle timing for low power pixel readout
Zheng Yang, San Jose, CA (US); and Ling Fu, Santa Clara, CA (US)
Assigned to OmniVision Technologies, Inc., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Apr. 6, 2022, as Appl. No. 17/714,738.
Int. Cl. H04N 25/75 (2023.01); H04N 25/709 (2023.01); H04N 25/772 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/75 (2023.01) [H04N 25/709 (2023.01); H04N 25/772 (2023.01)] 18 Claims
OG exemplary drawing
 
1. A pixel readout circuit, comprising:
an analog to digital converter coupled to the bitline output of the pixel circuit; and
a switch coupled between the bitline output of the pixel circuit and a reference voltage,
wherein the switch is configured to be pulsed on and off a first time to settle the bitline to the reference voltage prior to an autozero operation of the analog to digital converter for each readout of the pixel circuit,
wherein the switch is configured to be pulsed on and off a second time to settle the bitline to the reference voltage after the autozero operation and prior to a first analog to digital conversion operation of the analog to digital converter for each readout of the pixel circuit,
wherein the switch is configured to be pulsed on and off a third time to settle the bitline to the reference voltage after the first analog to digital conversion operation and prior to a second analog to digital conversion operation of the analog to digital converter for each readout of the pixel circuit.