US 11,683,276 B2
Quasi-output queue behavior of a packet switching device achieved using virtual output queue ordering independently determined for each output queue
Nadav Chachmon, Moshav Yaad (IL); Ofer Iny, Tel Aviv (IL); and Aviram Yeruchami, Kefar Sava (IL)
Assigned to Cisco Technology, Inc., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on May 20, 2021, as Appl. No. 17/303,136.
Prior Publication US 2022/0377026 A1, Nov. 24, 2022
Int. Cl. H04L 49/90 (2022.01); H04L 47/62 (2022.01)
CPC H04L 49/90 (2013.01) [H04L 47/62 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an egress interface group including a plurality of output queues, one or more virtual output queue (VOQ) schedulers, and one or more VOQ latency data structures stored in memory;
a plurality of ingress interface groups, with each particular ingress interface group of the plurality of ingress interface groups including for each particular output queue of the plurality of output queues, a particular virtual output queue (VOQ) storing packet entities for packets received by particular ingress interface group for said particular output queue, with said received packets being sent from the apparatus based on corresponding dequeuing orders from the plurality of output queues; and
one or more communication mechanisms providing data path communications between each of ingress interface groups and the egress interface group, including communicating, to the egress interface group, said packet entities dequeued from said VOQs as identified by next VOQ identifiers determined by said VOQ schedulers;
wherein for each specific output queue of the plurality of output queues, said VOQ schedulers repeatedly determine a specific next VOQ identifier for said specific output queue and maintains latency information of said VOQs of said specific output queue in said VOQ latency data structures independent of maintained latency information of VOQs of other of said output queues.