US 11,683,093 B2
Wavelength dispersion compensation apparatus, optical receiving apparatus, wavelength dispersion compensation method and computer program
Masanori Nakamura, Musashino (JP); Seiji Okamoto, Musashino (JP); Kengo Horikoshi, Musashino (JP); Shuto Yamamoto, Musashino (JP); Takayuki Kobayashi, Musashino (JP); Yoshiaki Kisaka, Musashino (JP); and Masahito Tomizawa, Musashino (JP)
Assigned to Nippon Telegraph and Telephone Corporation, Tokyo (JP)
Appl. No. 17/614,686
Filed by Nippon Telegraph and Telephone Corporation, Tokyo (JP)
PCT Filed Jun. 6, 2019, PCT No. PCT/JP2019/022560
§ 371(c)(1), (2) Date Nov. 29, 2021,
PCT Pub. No. WO2020/245984, PCT Pub. Date Dec. 10, 2020.
Prior Publication US 2022/0224415 A1, Jul. 14, 2022
Int. Cl. H04B 10/06 (2006.01); H04B 10/2513 (2013.01); H03H 17/02 (2006.01); H04B 10/61 (2013.01)
CPC H04B 10/2513 (2013.01) [H03H 17/0213 (2013.01); H04B 10/61 (2013.01); H04B 10/616 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A wavelength dispersion compensation apparatus comprising:
a block divider configured to segment an electric digital received signal obtained from a received optical signal into blocks of a certain length with an overlap of a length determined in advance with an adjacent block and output the blocks;
a Fourier transformer configured to perform Fourier transformation for each of the blocks output by the block divider;
a coefficient multiplier configured to store a plurality of the blocks converted by the Fourier transformer consecutively in time series, apply a coefficient determined based on a wavelength dispersion compensation amount according to one of frequency positions and a delay amount according to one of the frequency positions and one of time positions to frequency component values included in the plurality of the blocks that are stored, and generate blocks with the coefficient applied, the blocks with the coefficient applied being obtained by adding up frequency component values with the coefficient applied for each of the frequency positions;
an inverse Fourier transformer configured to perform inverse Fourier transformation on the blocks with the coefficient applied that are generated by the coefficient multiplier; and
an overlap cutter configured to remove a part of the overlap from the blocks with the coefficient applied that are converted by the inverse transformer,
wherein each of the block divider, the Fourier transformer, the coefficient multiplier, the inverse Fourier transformer and the overlap cutter is implemented by:
i) computer executable instructions executed by at least one processor,
ii) at least one circuitry or
iii) a combination of computer executable instructions executed by at least one processor and at least one circuitry.