US 11,682,714 B2
Inner spacer features for multi-gate transistors
Bone-Fong Wu, Hsinchu (TW); Chih-Hao Yu, Tainan (TW); and Chia-Pin Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 28, 2022, as Appl. No. 17/706,296.
Application 17/706,296 is a continuation of application No. 16/937,164, filed on Jul. 23, 2020, granted, now 11,289,584.
Claims priority of provisional application 63/015,198, filed on Apr. 24, 2020.
Prior Publication US 2022/0223718 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/66553 (2013.01) [H01L 29/0653 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/7853 (2013.01); H01L 21/0214 (2013.01); H01L 21/0228 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a nanostructure including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion;
a first inner spacer feature disposed over and in contact with the first connection portion;
a second inner spacer feature disposed under and in contact with the first connection portion; and
a gate structure wrapping around the channel portion of the nanostructure,
wherein the nanostructure further comprises a first ridge extending upward along a vertical direction from an interface between the channel portion and the first connection portion.