US 11,682,678 B2
Liquid crystal display device and method for manufacturing the same
Shunpei Yamazaki, Tokyo (JP); and Kaoru Hatano, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jul. 7, 2022, as Appl. No. 17/859,054.
Application 17/859,054 is a continuation of application No. 17/331,826, filed on May 27, 2021, granted, now 11,417,688.
Application 17/331,826 is a continuation of application No. 16/724,666, filed on Dec. 23, 2019, granted, now 11,024,655, issued on Jun. 1, 2021.
Application 16/724,666 is a continuation of application No. 15/916,362, filed on Mar. 9, 2018, granted, now 10,522,572, issued on Dec. 31, 2019.
Application 15/916,362 is a continuation of application No. 15/088,200, filed on Apr. 1, 2016, granted, now 9,917,112, issued on Mar. 13, 2018.
Application 15/088,200 is a continuation of application No. 14/023,515, filed on Sep. 11, 2013, granted, now 9,305,944, issued on Apr. 5, 2016.
Application 14/023,515 is a continuation of application No. 13/227,092, filed on Sep. 7, 2011, granted, now 8,558,960, issued on Oct. 15, 2013.
Claims priority of application No. 2010-204930 (JP), filed on Sep. 13, 2010.
Prior Publication US 2022/0344375 A1, Oct. 27, 2022
Int. Cl. G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/124 (2013.01) [G02F 1/1333 (2013.01); G02F 1/1343 (2013.01); G02F 1/136213 (2013.01); H01L 27/1225 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); G02F 1/136227 (2013.01); G02F 1/136231 (2021.01); G02F 2201/50 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel portion comprising:
a first conductive layer comprising a region in contact with an insulating surface;
a first insulating layer comprising a region in contact with an upper surface of the first conductive layer;
a first oxide semiconductor layer comprising a region in contact with an upper surface of the first insulating layer, the first oxide semiconductor layer comprising a channel formation region of a transistor;
a second conductive layer comprising a region in contact with an upper surface of the first oxide semiconductor layer;
a second insulating layer over the first oxide semiconductor layer and the second conductive layer; and
a third conductive layer electrically connected to the second conductive layer, the third conductive layer comprising a region over the second insulating layer; and
a connecting portion comprising:
a fourth conductive layer comprising a region in contact with the insulating surface, the fourth conductive layer comprising the same material as the first conductive layer;
the first insulating layer comprising a region in contact with an upper surface of the fourth conductive layer;
a second oxide semiconductor layer comprising a region in contact with the upper surface of the first insulating layer; and
a fifth conductive layer over the second oxide semiconductor layer, the fifth conductive layer comprising the same material as the third conductive layer,
wherein the first conductive layer is configured to serve as a gate electrode of the transistor,
wherein the second conductive layer is configured to serve as one of a source electrode and a drain electrode of the transistor,
wherein each of the first conductive layer and the fourth conductive layer comprises a stacked structure comprising a titanium layer and a copper layer over the titanium layer,
wherein the first insulating layer and the second oxide semiconductor layer comprise a contact hole, and
wherein the fifth conductive layer is electrically connected to the fourth conductive layer through the contact hole.