	US 11,682,667 B2
	Memory cell including cell transistor including control gate and charge accumulation layer
Shunpei Yamazaki, Setagaya (JP); and Hajime Kimura, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 16/623,657
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Jun. 21, 2018, PCT No. PCT/IB2018/054566 § 371(c)(1), (2) Date Dec. 17, 2019, PCT Pub. No. WO2019/003060, PCT Pub. Date Jan. 3, 2019.
Claims priority of application No. JP2017-125011 (JP), filed on Jun. 27, 2017.
Prior Publication US 2020/0203339 A1, Jun. 25, 2020
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/088 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01)

CPC H01L 27/088 (2013.01) [H01L 21/76846 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01)]

9 Claims

1. A semiconductor device comprising:

a first insulator;

a second insulator;

a third insulator;

a fourth insulator;

a first conductor;

a second conductor; and

a first semiconductor,

wherein the first semiconductor comprises a first surface and a second surface,

wherein a first side surface and a second side surface of the first insulator are positioned in a region overlapping the first surface of the first semiconductor with the first conductor therebetween,

wherein a first side surface of the first conductor is in direct contact with the first surface of the first semiconductor,

wherein the first side surface of the first insulator is in contact with a second side surface of the first conductor,

wherein the second insulator is in contact with the second side surface of the first insulator, a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor,

wherein the third insulator is positioned in a region overlapping the second surface of the first semiconductor with the second insulator therebetween,

wherein the fourth insulator is in contact with the third insulator,

wherein the second conductor is positioned in a region overlapping the second surface of the first semiconductor with the second insulator, the third insulator, and the fourth insulator therebetween,

wherein the second conductor is in contact with the fourth insulator,

wherein the third insulator is configured to accumulate charge, and

wherein a tunnel current is induced between the second surface of the first semiconductor and the third insulator with the second insulator therebetween by supply of a potential to the second conductor.