US 11,682,651 B2
Bump-on-trace interconnect
Chen-Hua Yu, Hsinchu (TW); and Chen-Shien Chen, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 23, 2020, as Appl. No. 17/102,073.
Application 15/065,632 is a division of application No. 13/653,618, filed on Oct. 17, 2012, granted, now 9,299,674, issued on Mar. 29, 2016.
Application 17/102,073 is a continuation of application No. 16/710,780, filed on Dec. 11, 2019, granted, now 10,847,493.
Application 16/710,780 is a continuation of application No. 15/997,124, filed on Jun. 4, 2018, granted, now 10,510,710, issued on Dec. 17, 2019.
Application 15/997,124 is a continuation of application No. 15/065,632, filed on Mar. 9, 2016, granted, now 9,991,224, issued on Jun. 5, 2018.
Claims priority of provisional application 61/625,980, filed on Apr. 18, 2012.
Prior Publication US 2021/0074673 A1, Mar. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01)
CPC H01L 24/81 (2013.01) [H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/131 (2013.01); H01L 2224/1308 (2013.01); H01L 2224/13017 (2013.01); H01L 2224/13076 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/16058 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06593 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/381 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first substrate having a conductive land;
a conductive bump attached to the conductive land and extending away from the conductive land, wherein an end surface of the conductive bump distal from the conductive land has a first width;
a second substrate;
a conductive trace on a first side of the second substrate facing the first substrate, wherein a first surface of the conductive trace distal from the second substrate has a second width smaller than the first width, wherein a first sidewall of the conductive trace has a first height, wherein the end surface of the conductive bump is spaced apart from the first surface of the conducive trace by a first distance smaller than the first height; and
a conductive material bonding the conductive bump to the conductive trace, wherein the conductive material extends along and covers the first sidewall of the conductive trace by at least half the first height.