US 11,682,636 B2
Info structure and method forming same
Po-Han Wang, Hsinchu (TW); Yu-Hsiang Hu, Hsinchu (TW); Hung-Jui Kuo, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 29, 2021, as Appl. No. 17/215,297.
Application 16/403,878 is a division of application No. 15/939,615, filed on Mar. 29, 2018, granted, now 10,283,461, issued on May 7, 2019.
Application 17/215,297 is a continuation of application No. 16/732,529, filed on Jan. 2, 2020, granted, now 10,964,650.
Application 16/732,529 is a continuation of application No. 16/403,878, filed on May 6, 2019, granted, now 10,529,675, issued on Jan. 7, 2020.
Claims priority of provisional application 62/589,892, filed on Nov. 22, 2017.
Prior Publication US 2021/0217709 A1, Jul. 15, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/58 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/485 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 21/561 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1082 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
placing a plurality of conductive pins over a carrier;
placing a device die over the carrier;
encapsulating the plurality of conductive pins and the device die in an encapsulant, wherein a top layer of the encapsulant covers the device die and the plurality of conductive pins;
forming openings in the top layer of the encapsulant to reveal the plurality of conductive pins and conductive features of the device die; and
forming a first plurality of redistribution lines extending into the openings to contact the conductive features of the device die, wherein the device die, the plurality of conductive pins, and the first plurality of redistribution lines form parts of a package.