US 11,682,593 B2
Interposer test structures and methods
Tzuan-Horng Liu, Longtan Township (TW); Chen-Hua Yu, Hsinchu (TW); Hsien-Pin Hu, Zhubei (TW); Tzu-Yu Wang, Taipei (TW); Wei-Cheng Wu, Hsinchu (TW); Shang-Yun Hou, Jubei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2020, as Appl. No. 16/932,948.
Application 14/846,605 is a division of application No. 13/198,223, filed on Aug. 4, 2011, granted, now 9,128,123, issued on Sep. 8, 2015.
Application 16/932,948 is a continuation of application No. 16/148,169, filed on Oct. 1, 2018, granted, now 10,734,295.
Application 16/148,169 is a continuation of application No. 15/449,683, filed on Mar. 3, 2017, granted, now 10,090,213, issued on Oct. 2, 2018.
Application 15/449,683 is a continuation of application No. 14/846,605, filed on Sep. 4, 2015, granted, now 9,589,857, issued on Mar. 7, 2017.
Claims priority of provisional application 61/492,989, filed on Jun. 3, 2011.
Prior Publication US 2020/0350221 A1, Nov. 5, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/48 (2006.01); H01L 21/66 (2006.01); H01L 23/498 (2006.01); G01R 1/073 (2006.01); H01L 23/522 (2006.01); H01L 23/58 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01)
CPC H01L 22/32 (2013.01) [G01R 1/07378 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 22/30 (2013.01); H01L 22/34 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5226 (2013.01); H01L 23/585 (2013.01); H01L 21/561 (2013.01); H01L 21/6835 (2013.01); H01L 2221/68331 (2013.01); H01L 2224/05001 (2013.01); H01L 2224/056 (2013.01); H01L 2224/05026 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an integrated circuit die, the integrated circuit die comprising a plurality of die contact pads and a plurality of die interconnects, each of the plurality of die interconnects electrically coupling two of the plurality of die contact pads to each other; and
an interposer bonded to the integrated circuit die, the interposer comprising a plurality of interposer contact pads, a plurality of interposer interconnects, a first test connection, and a second test connection, wherein:
each of the plurality of interposer interconnects electrically couple two of the plurality of interposer contact pads to each other;
each of the plurality of interposer contact pads are coupled to corresponding ones of the plurality of die contact pads; and
the plurality of interposer interconnects, the plurality of interposer contact pads, the plurality of die contact pads, and the plurality of die interconnects form a daisy chain electrically interposed between the first test connection and the second test connection.