US 11,682,504 B2
Method for producing chip varistor and chip varistor
Satoshi Goto, Tokyo (JP); Naoyoshi Yoshida, Tokyo (JP); Takeshi Yanata, Tokyo (JP); Takeshi Oyanagi, Tokyo (JP); Daiki Suzuki, Tokyo (JP); Shin Kagaya, Tokyo (JP); Masayuki Uchida, Tokyo (JP); and Yusuke Imai, Tokyo (JP)
Assigned to TDK CORPORATION, Tokyo (JP)
Filed by TDK CORPORATION, Tokyo (JP)
Filed on Mar. 7, 2022, as Appl. No. 17/687,752.
Application 17/687,752 is a continuation of application No. 17/230,100, filed on Apr. 14, 2021, granted, now 11,302,464.
Claims priority of application No. JP2020-073502 (JP), filed on Apr. 16, 2020.
Prior Publication US 2022/0189665 A1, Jun. 16, 2022
Int. Cl. H01C 7/10 (2006.01); H01C 7/102 (2006.01); H01C 7/108 (2006.01)
CPC H01C 7/1006 (2013.01) [H01C 7/102 (2013.01); H01C 7/108 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A chip varistor comprising:
an element body;
first and second internal electrodes (i) in the element body, (ii) that oppose each other in a first direction, (iii) spaced from each other in the first direction, and (iv) that are connected to different external electrodes; and
at least one intermediate conductor (i) in the element body between the first and second internal electrodes, (ii) that opposes the first and second internal electrodes in the first direction and (iii) spaced from the first and second internal electrodes in the first direction, wherein:
the first and second internal electrodes overlap in the first direction to define an overlapping region having a first outer edge when viewed in the first direction;
the at least one intermediate conductor includes a second outer edge when viewed in the first direction; and
the second outer edge is spaced inwardly from the first outer edge in the overlapping region when viewed in the first direction.