US 11,681,846 B1
Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs
Xiaojian Yang, Santa Clara, CA (US); Frederic Revenu, San Carlos, CA (US); Dinesh D. Gaitonde, Fremont, CA (US); and Amit Gupta, Los Altos, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Jan. 12, 2021, as Appl. No. 17/147,163.
Int. Cl. G06F 30/343 (2020.01); G06F 30/347 (2020.01)
CPC G06F 30/343 (2020.01) [G06F 30/347 (2020.01)] 4 Claims
OG exemplary drawing
 
1. A method of FPGA compilation for a multiple level FPGA, comprising:
partitioning an FPGA netlist into a first set of sub-FPGA netlists, such that each sub-FPGA netlist in the set fits within an upper level dynamic sub-FPGA region of a plurality of upper level dynamic sub-FPGA regions;
for each sub-FPGA netlist in the set:
further partitioning the sub-FPGA netlist into sub-sub-FPGA netlists;
determining if a number of interconnects between the sub-sub-FPGA netlists is below a pre-defined capacity;
adopting the further partitioning if an interconnects capacity is met, and assigning the sub-sub netlists to a lower level dynamic sub-FPGA region; and
rejecting the further partitioning if the interconnect capacity is exceeded, and assigning the sub-FPGA netlist to the upper level dynamic sub-FPGA region;
obtaining a final partitioning comprising upper level sub-FPGA netlists and lower level sub-FPGA netlists;
using at least one of the upper level sub-FPGA netlists or the lower level sub-FPGA netlists to obtain a corresponding set of sub-FPGA bitstreams; and
loading the set of sub-FPGA bitstreams into the FPGA.