CPC G06F 30/343 (2020.01) [G06F 30/347 (2020.01)] | 4 Claims |
1. A method of FPGA compilation for a multiple level FPGA, comprising:
partitioning an FPGA netlist into a first set of sub-FPGA netlists, such that each sub-FPGA netlist in the set fits within an upper level dynamic sub-FPGA region of a plurality of upper level dynamic sub-FPGA regions;
for each sub-FPGA netlist in the set:
further partitioning the sub-FPGA netlist into sub-sub-FPGA netlists;
determining if a number of interconnects between the sub-sub-FPGA netlists is below a pre-defined capacity;
adopting the further partitioning if an interconnects capacity is met, and assigning the sub-sub netlists to a lower level dynamic sub-FPGA region; and
rejecting the further partitioning if the interconnect capacity is exceeded, and assigning the sub-FPGA netlist to the upper level dynamic sub-FPGA region;
obtaining a final partitioning comprising upper level sub-FPGA netlists and lower level sub-FPGA netlists;
using at least one of the upper level sub-FPGA netlists or the lower level sub-FPGA netlists to obtain a corresponding set of sub-FPGA bitstreams; and
loading the set of sub-FPGA bitstreams into the FPGA.
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