CPC G06F 17/16 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); H03M 1/662 (2013.01)] | 20 Claims |
1. A method for performing vector-matrix multiplication, the method comprising:
converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital-to-analog converters (DACs);
sequentially performing, using an analog vector matrix multiplier, a vector-matrix multiplication operation using a weighting matrix for each bit-order of the plurality of analog signals;
for each sequentially performed vector-matrix multiplication operation, operating a switch in a plurality of switches that corresponds to a current bit-order, wherein:
operating the switch causes a value corresponding to an output of the analog vector matrix multiplier to be stored on a capacitor in a plurality of capacitors, and the capacitor corresponds to the current bit-order; and
a time interval during the switch is operated is non-uniform with respect to time intervals during which other switches in the plurality of switches are operated, and the time interval is based at least in part on a settling time of the capacitor; and
performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.
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