US 11,681,776 B2
Adaptive settling time control for binary-weighted charge redistribution circuits
Xiaofeng Zhang, San Jose, CA (US); and She-Hwa Yen, Mountain View, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Nov. 7, 2020, as Appl. No. 17/92,227.
Claims priority of provisional application 63/089,491, filed on Oct. 8, 2020.
Prior Publication US 2022/0114233 A1, Apr. 14, 2022
Int. Cl. G06F 17/16 (2006.01); H03M 1/66 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01)
CPC G06F 17/16 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); H03M 1/662 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for performing vector-matrix multiplication, the method comprising:
converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital-to-analog converters (DACs);
sequentially performing, using an analog vector matrix multiplier, a vector-matrix multiplication operation using a weighting matrix for each bit-order of the plurality of analog signals;
for each sequentially performed vector-matrix multiplication operation, operating a switch in a plurality of switches that corresponds to a current bit-order, wherein:
operating the switch causes a value corresponding to an output of the analog vector matrix multiplier to be stored on a capacitor in a plurality of capacitors, and the capacitor corresponds to the current bit-order; and
a time interval during the switch is operated is non-uniform with respect to time intervals during which other switches in the plurality of switches are operated, and the time interval is based at least in part on a settling time of the capacitor; and
performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.