US 11,681,530 B2
Apparatuses, methods, and systems for hashing instructions
Regev Shemy, Kiryat Ata (IL); Zeev Sperber, Zichron Yackov (IL); Wajdi Feghali, Boston, MA (US); Vinodh Gopal, Westborough, MA (US); Amit Gradstein, Binyamina (IL); Simon Rubanovich, Haifa (IL); Sean Gulley, Sudbury, MA (US); Ilya Albrekht, Tempe, AZ (US); Jacob Doweck, Haifa (IL); Jose Yallouz, Haifa (IL); and Ittai Anati, Ramat Hasharon (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 7, 2022, as Appl. No. 17/688,728.
Application 17/688,728 is a continuation of application No. 17/537,373, filed on Nov. 29, 2021, granted, now 11,567,772.
Application 17/537,373 is a continuation of application No. 17/087,536, filed on Nov. 2, 2020, granted, now 11,188,335, issued on Nov. 30, 2021.
Application 17/087,536 is a continuation of application No. 16/370,459, filed on Mar. 29, 2019, granted, now 10,824,428, issued on Nov. 3, 2020.
Prior Publication US 2022/0188114 A1, Jun. 16, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); H04L 9/06 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30196 (2013.01); G06F 9/3887 (2013.01); H04L 9/0643 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element; and
an execution circuit coupled with the decode circuit, the execution circuit to perform operations corresponding to the first instruction, including to:
generate a result, the result to include:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and
store the result in the first vector register.