| US 7,552,314 B2 | ||
| Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address | ||
| Anatoly Gelman, San Diego, Calif. (US); and Russell Schnapp, San Diego, Calif. (US) | ||
| Assigned to STMicroelectronics, Inc., Carrollton, Tex. (US) | ||
| Filed on Oct. 17, 2005, as Appl. No. 11/252,029. | ||
| Application 11/252029 is a continuation of application No. 09/429590, filed on Oct. 28, 1999, granted, now 6,957,327. | ||
| Claims priority of provisional application 60/114297, filed on Dec. 31, 1998. | ||
| Prior Publication US 2006/0036836 A1, Feb. 16, 2006 | ||
| Int. Cl. G06F 9/38 (2006.01) | ||
| U.S. Cl. 712—206 [712/238; 712/239; 712/240] | 17 Claims |
| 1. A method for use in performing branch prediction in a processor, comprising:
storing in a memory a block comprising multiple instruction;
storing, in a block entry of a fetch-block branch target buffer, a length value representing a size of a first fetch-block,
a value representing a branch type, and a value representing a branch prediction;
determining whether a fetch address corresponds to the block entry; and
according to the value representing the branch prediction, selecting one of: the length value associated with the first fetch-block
and a maximum length; and
fetching a number of instructions corresponding to the selected length from the memory using the fetch address.
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