| US 7,552,288 B2 | ||
| Selectively inclusive cache architecture | ||
| Ravishankar Iyer, Portland, Oreg. (US); Li Zhao, Beaverton, Oreg. (US); Srihari Makineni, Portland, Oreg. (US); and Donald Newell, Portland, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Aug. 14, 2006, as Appl. No. 11/503,777. | ||
| Prior Publication US 2008/0040555 A1, Feb. 14, 2008 | ||
| Int. Cl. G06F 12/08 (2006.01) | ||
| U.S. Cl. 711—141 [711/122; 711/124] | 14 Claims |
| 1. A method comprising:
maintaining data in a first level cache non-inclusively with a second level cache coupled to the first level cache; and
maintaining at least a portion of directory information associated with the data in the first level cache and present in the
first level cache inclusive with a directory portion of the second level cache while maintaining the directory portion of
the second level cache exclusive with a data portion of the second level cache.
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