an output terminal that outputs the set potentials;

a boosting circuit that boosts, in response to an input of a boosting clock signal, a voltage supplied from a power supply and outputs the voltage to the output terminal;

a control circuit that outputs the control signals;

a voltage detecting circuit that detects an output potential outputted from the output terminal, compares a first reference potential and the output potential to output a first flag signal including information about a comparison result, and compares a second reference potential higher than the first reference potential and the output potential to output a second flag signal for instructing activation or deactivation of the boosting circuit;

a clock generating circuit that outputs a reference clock signal in response to an input of the first flag signal when the output potential is lower than the first reference potential, and outputs a frequency divided clock signal obtained by dividing the reference clock signal when the output potential is higher than the first reference potential; and

a logic circuit that performs an operation based on the second flag signal and one of the reference clock signal and the frequency divided clock signal that are outputted from the clock generating circuit, and outputs the boosting clock signal for activating the boosting circuit;

wherein the voltage detecting circuit changes levels of the first reference potential and the second reference potential in response to inputs of the control signals, and

the clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals.