| US 7,551,493 B2 | ||
| Data processing device | ||
| Akira Kato, Tachikawa (Japan); Toshihiro Tanaka, Akiruno (Japan); and Takashi Yamaki, Kodaira (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jun. 21, 2007, as Appl. No. 11/766,341. | ||
| Application 11/766341 is a division of application No. 11/140741, filed on Jun. 01, 2005, granted, now 7,248,504. | ||
| Prior Publication US 2007/0285984 A1, Dec. 13, 2007 | ||
| Int. Cl. G11C 11/30 (2006.01) | ||
| U.S. Cl. 365—185.29 [365/185.05; 365/185.15] | 9 Claims |
| 1. A data processing device comprising:
a nonvolatile memory provided with a memory array; and
a controller,
wherein the memory array includes a plurality of nonvolatile memory cells each having a pair of a first MOS transistor and
a second MOS transistor, the first MOS transistor, which is used for data storage, having a charge retention layer and a memory
gate, and the second MOS transistor having a control gate to selectively connect the first MOS transistor to a bit line, and
wherein the controller controls the bit line potential level in accordance with whether to supply electric current between
a drain and a source of a nonvolatile memory cell of the plurality of nonvolatile memory cells, and controls the polarity
of high voltage applied to the memory gate to select either emission of electrons from, or injection of electrons into, the
charge retention layer of the nonvolatile memory cell to which the current is supplied.
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