| US 7,551,485 B2 | ||
| Semiconductor memory device | ||
| Mitsuaki Honma, Yokohama (Japan); and Noboru Shibata, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 21, 2008, as Appl. No. 12/106,892. | ||
| Application 12/106892 is a continuation of application No. 11/352363, filed on Feb. 13, 2006, granted, now 7,362,623. | ||
| Claims priority of application No. 2005-090860 (JP), filed on Mar. 28, 2005. | ||
| Prior Publication US 2008/0198659 A1, Aug. 21, 2008 | ||
| Int. Cl. G11C 16/06 (2006.01) | ||
| U.S. Cl. 365—185.21 [365/185.12; 365/189.09; 365/189.06; 365/207] | 5 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arranged therein, each of the memory cells capable of being connected
to a bit line for data read or data write;
a sense amplifier circuit configured to read data of the memory cell array via the bit line; and
a controller configured to control the sense amplifier circuit,
the sense amplifier circuit further comprising:
a clamp transistor connected between the bit line and a first node to transfer a voltage of the bit line to the first node;
a first latch circuit capable of being connected to the first node to store data in a second node;
a second latch circuit capable of being connected between the first node and a data line for inputting/outputting data, to
store data in a third node;
a first write-back circuit having a fourth node and configured to write back data stored in the second node to the first node
via the fourth node, and to perform data addition/subtraction between the first node and the fourth node; and
a second write-back circuit having a fifth node and configured to write back data stored in the second node to the first node
via the fifth node, and to perform data addition/subtraction between the first node and the fifth node.
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