US 7,551,472 B2
Ferroelectric semiconductor memory device
Susumu Shuto, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Aug. 29, 2007, as Appl. No. 11/896,044.
Claims priority of application No. 2006-233273 (JP), filed on Aug. 30, 2006.
Prior Publication US 2008/0055962 A1, Mar. 06, 2008
Int. Cl. G11C 11/00 (2006.01)
U.S. Cl. 365—145  [365/173] 11 Claims
OG exemplary drawing
 
1. A ferroelectric semiconductor memory device comprising:
a memory cell block including a plurality of ferroelectric memory cells connected in series, each memory cell including a ferroelectric capacitor for holding a charge and a transistor connected in parallel with the ferroelectric capacitor;
word lines connected to the respective transistors;
a selection transistor connected to one end of the block;
a bit line connected to the selection transistor;
a plate line connected to another end of the block; and
a control circuit for changing potentials of the word line and the bit line,
with the potential of the plate line being held constant, the potential of the word line being changed, thereby erasing information or writing information to the ferroelectric memory cells,
the information of the memory cells included in the block being erased by sequentially executing steps comprising:
a first step of turning on, with the selection transistor being held off, all of the transistors;
a second step of switching, with the selection transistor being held off, one of the transistors from on to off; and
a third step of switching, with the one of the transistors being held off, the selection transistor from off to on,
the potential of the bit line and the potential of the plate line being held constant during the first step to the third step.