| US 7,551,009 B2 | ||
| High-speed divider with reduced power consumption | ||
| Akhil K. Garlapati, Wobum, Mass. (US); Lizhong Sun, Nashua, N.H. (US); and Douglas F. Pastorello, Hudson, N.H. (US) | ||
| Assigned to Silicon Laboratories Inc., Austin, Tex. (US) | ||
| Filed on Feb. 28, 2007, as Appl. No. 11/680,016. | ||
| Prior Publication US 2008/0204088 A1, Aug. 28, 2008 | ||
| Int. Cl. H03K 21/00 (2006.01); H03K 23/00 (2006.01); H03K 25/00 (2006.01) | ||
| U.S. Cl. 327—115 | 24 Claims |
| 1. A method for dividing a signal having a first frequency by a divide ratio to generate a lower frequency signal comprising:
selecting, based at least in part on the divide ratio, a first pulse width of at least one signal having a second frequency
and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least
one signal having a second pulse width;
selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal,
the at least one of the plurality of pulse-width control circuits including a first pulse-width control circuit to generate
a first signal having the first pulse width, second frequency, and first phase, the first signal corresponding to a select
circuit output signal having a first phase; and
selecting at least one other of the plurality of pulse-width control circuits to be powered-off.
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