| US 7,550,996 B2 | ||
| Structured integrated circuit device | ||
| Zvi Or-Bach, San Jose, Calif. (US); Petrica Avram, Iasi (Romania); Romeo Iacobut, Iasi (Romania); Adrian Apostol, Iasi (Romania); Ze'ev Wurman, Palo Alto, Calif. (US); Adam Levinthal, Redwood City, Calif. (US); and Richard Zeman, San Jose, Calif. (US) | ||
| Assigned to Easic Corporation, Santa Clara, Calif. (US) | ||
| Filed on Mar. 03, 2006, as Appl. No. 11/366,528. | ||
| Application 11/366528 is a continuation of application No. 10/899020, filed on Jul. 27, 2004, granted, now 7,098,691. | ||
| Prior Publication US 2006/0164121 A1, Jul. 27, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 7/38 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—39 [326/41; 326/101] | 24 Claims |
| 1. A semiconductor device comprising:
a logic array, said logic array including a multiplicity of logic cells, each logic cell comprising at least one look-up table,
said logic array further including metal and via connection layers overlying the multiplicity of logic cells to provide at
least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect
is customized by a custom via layer; and
a multiplicity of device-customized I/O cells, wherein said device-customized I/O cells are customized by directly connecting
at least two of a multiplicity of devices within each I/O cell using said custom via layer.
|