| US 7,550,982 B2 | ||
| Semiconductor device test method for comparing a first area with a second area | ||
| Keizo Yamada, Tokyo (Japan) | ||
| Assigned to Topcon Corporation, Itabashi-Ku, Tokyo (Japan) | ||
| Filed on Oct. 25, 2007, as Appl. No. 11/976,563. | ||
| Application 11/976563 is a division of application No. 11/437375, filed on May 19, 2006, granted, now 7,420,379. | ||
| Application 11/437375 is a division of application No. 11/150967, filed on Jun. 13, 2005, granted, now 7,049,834. | ||
| Application 11/150967 is a division of application No. 10/868581, filed on Jun. 15, 2004, granted, now 6,914,444. | ||
| Application 10/868581 is a division of application No. 09/865528, filed on May 29, 2001, granted, now 6,809,534. | ||
| Claims priority of application No. 2000-160769 (JP), filed on May 30, 2000. | ||
| Prior Publication US 2008/0079447 A1, Apr. 03, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G01R 31/02 (2006.01) | ||
| U.S. Cl. 324—751 [324/765] | 5 Claims |
| 1. A method of testing a semiconductor wafer having a first area, wherein the first area includes a plurality of contacts
or via holes arranged in a pattern, the method comprising:
scanning an electron beam across the first area;
measuring a first current waveform generated in response to the scanning of the electron beam across the first area, while
obtaining first coordinates information indicative of irradiating positions of the electron beam in the first area;
determining first locations of the contacts or via holes in the first area using the first current waveform and the first
coordinates information; and
comparing the first locations with second locations of a plurality of contacts or via holes which are arranged in a second
area in the same or substantially the same pattern as the pattern of the contacts or via holes in the first area to detect
a difference therebetween, wherein the second locations are preliminarily obtained.
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