a first power supply line which extends in a first direction at one side of a semiconductor chip, and to which a first power supply voltage is to be applied;

a second power supply line which is disposed at one side of the first power supply line, which extends in the first direction, and to which a second power supply voltage higher than the first power supply voltage or a third power supply voltage higher than the first power supply voltage and lower than the second power supply voltage is to be applied;

a third power supply line which is disposed at the other side of the first power supply line, which extends in the first direction, and to which the second or the third power supply voltage is to be applied;

a first pad array to which an input signal from an external point is supplied, the first pad array being disposed between the first and the second power supply lines, and including a plurality of first pads which are disposed in the first direction;

a second pad array to which an output signal to the external point is supplied, the second pad array being disposed between the first and the third power supply lines, the second pad array including a plurality of second pads which are disposed in the first direction;

a plurality of first buffer circuits which are operated by a voltage between the first and second power supply lines, each of the first buffer circuit being disposed between the first pads, and including a first NMOS transistor and a first PMOS transistor which are connected to one of the second pads; and

a plurality of second buffer circuits which are operated by a voltage between the first and third power supply lines, each of the second buffer circuit being disposed between the second pads, and including a second NMOS transistor and a second PMOS transistor which are connected to one of the first pads.