| US 7,550,765 B2 | ||
| Semiconductor device and fabrication method thereof | ||
| Shunpei Yamazaki, Setagaya (Japan); and Satoshi Teramoto, Ayase (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken (Japan) | ||
| Filed on Apr. 04, 2006, as Appl. No. 11/396,718. | ||
| Application 11/396718 is a division of application No. 09/334646, filed on Jun. 17, 1999, abandoned. | ||
| Application 09/334646 is a division of application No. 08/938310, filed on Sep. 26, 1997, granted, now 5,959,313. | ||
| Application 08/938310 is a division of application No. 08/513090, filed on Aug. 09, 1995, granted, now 5,731,613. | ||
| Claims priority of application No. 6-218077 (JP), filed on Aug. 19, 1994. | ||
| Prior Publication US 2006/0175612 A1, Aug. 10, 2006 | ||
| Int. Cl. H01L 27/15 (2006.01) | ||
| U.S. Cl. 257—57 [257/59; 257/72; 257/84; 257/E31.083] | 40 Claims |
| 1. A display device comprising:
an active matrix region; and
a peripheral circuit comprising at least three thin film transistors formed over a substrate, wherein the at least three thin
film transistors comprise:
three channel-forming regions in one common active layer;
a common gate wiring adjacent to the one common active layer;
a common source wiring electrically connected to the one common active layer; and
a common drain wiring electrically connected to the one common active layer,
wherein the at least three thin film transistors are electrically connected in parallel with each other through the common
gate wiring, the common source wiring and the common drain wiring.
|