| US 7,550,342 B2 | ||
| Nonvolatile semiconductor memory device and method of manufacturing the same | ||
| Koichi Matsuno, Mie-gun (Japan); and Tadashi Iguchi, Yokkaichi (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 06, 2007, as Appl. No. 11/682,566. | ||
| Application 11/682566 is a division of application No. 11/137652, filed on May 26, 2005, granted, now 7,208,801. | ||
| Claims priority of application No. 2004-159952 (JP), filed on May 28, 2004. | ||
| Prior Publication US 2007/0148854 A1, Jun. 28, 2007 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—211 | 5 Claims |
| 1. A method of manufacturing a nonvolatile semiconductor memory device whose gate structure of a transistor other than a memory
cell transistor has a same stacked gate structure as the memory cell transistor, the method of making the gate structure comprising:
successively depositing a first insulation film, a first doped polysilicon film and a second insulation film on a semiconductor
substrate;
depositing a second undoped polysilicon film on the second insulation film;
selectively removing the second undoped polysilicon film until the second insulation film is exposed, using a photoresist
film having a first opening with a first opening width;
depositing, after the photoresist film is removed, a third doped polysilicon film on a surface of the substrate;
selectively removing, by RIE, the third doped polysilicon film and the second insulation film in a vertical direction from
a bottom of the first opening, using the third doped polysilicon film as a spacer, to define a second opening with a second
opening width that is less than the first opening width; and
forming a conductive film on the surface of the substrate.
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