US 7,549,208 B2
	Method of mounting electronic circuit chip
Chikashi Okamoto, Kawasaki (Japan); Kazuo Takaragi, Kawasaki (Japan); Kazutaka Tsuji, Kokubunji (Japan); Mitsuo Usami, Kokubunji (Japan); Chizuko Yasunobu, Tokyo (Japan); Asahiko Sobe, Tokyo (Japan); Yasuhiro Tsunemi, Tokyo (Japan); and Hiroyuki Yagi, Tokyo (Japan)
Assigned to Hitachi, Ltd., Tokyo (Japan)
Filed on Oct. 20, 2003, as Appl. No. 10/687,753.
Application 10/687753 is a continuation of application No. 09/856758, filed on Sep. 14, 2001, granted, now 6,731,509.
Prior Publication US 2004/0156176 A1, Aug. 12, 2004
Int. Cl. H01Q 17/00 (2006.01)

U.S. Cl. 29—601

6 Claims

1. A method of mounting an electronic circuit chip together with another planar electric element to a foldable rectangular sheet having first sides and second sides which are not wider than the first sides, the electronic circuit chip-mounted sheet comprising a finished product that is foldable along at least one fold line of the foldable rectangular sheet, the method being characterized in that the electronic circuit chip is mounted to the foldable rectangular sheet at a position which is not on any one of a line passing through positions of one-half of the length of the first sides and being parallel with the second sides, lines passing respectively through positions of one-third or one-fourth of the length of the first sides and being parallel with the second sides, and a line passing through positions of one-half of the second sides and being parallel with the first sides.