| US 7,389,483 B2 | ||
| Method for auto enlarging bend portion width and computer readable recording medium for storing program thereof | ||
| Szu-Sheng Kang, Hsinchu (Taiwan) | ||
| Assigned to Faraday Technology Corp., Hsin-Chu (Taiwan) | ||
| Filed on Jun. 22, 2005, as Appl. No. 11/160,390. | ||
| Prior Publication US 2006/0294484 A1, Dec. 28, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—9 [716/10] | 36 Claims |
| 1. A method for automatically enlarging a width of a bend portion, for enlarging the width of the bend portion of a circuit
line in a circuit layout from an original width to an intended width, wherein two terminals of a center line of the bend portion
respectively are a first turn point and a second turn point of the circuit line, the method comprising:
performing a calculation based on the original width, the intended width, coordinates of the first turn point and the second
turn point, to obtain a plurality of coordinates of corner-points of a polygon, wherein a width of the polygon is the intended
width; and the step of performing the calculation comprises:
respectively selecting one point in each of two circuits coupled to the two terminals of the bend portion to respectively
set as a first determination point or a second determination point, wherein the bend portion in the circuit layout is 45 degree
bend portion; and
determining a calculation formula and obtaining the coordinates of the corner-points of the polygon, according to the first
determination point, the second determination point, the first turn point and the second turn point, wherein calculation and
obtaining the coordinates of the corner-points of the polygon include following an equation to get a coordinate difference
delta by
delta=[(0.707Wbend−0.499Wnormal)/RES+1]*RES,
wherein Wbend represents the intended width, Wnormal represents the original width, RES represents a resolution of the circuit layout,
adding the polygon into the original layout, overlapping with the bend portion, wherein the polygon, the bend portion, and
the whole circuit line are in the same layer.
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