| US 7,389,007 B2 | ||
| Semiconductor memory apparatus | ||
| Shuji Michinaka, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Mar. 27, 2006, as Appl. No. 11/389,264. | ||
| Application 11/389264 is a division of application No. 09/962267, filed on Sep. 26, 2001, granted, now 7,072,530. | ||
| Claims priority of application No. 2000-297172 (JP), filed on Sep. 28, 2000. | ||
| Prior Publication US 2006/0165299 A1, Jul. 27, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06K 9/54 (2006.01) | ||
| U.S. Cl. 382—305 [382/145] | 8 Claims |
| 1. A semiconductor memory apparatus comprising:
two bank areas each having one-port memories capable of performing writing and reading only with separate timings;
a writing control circuit configured to write data into said one-port memories in one bank area of said two bank areas; and
a reading control circuit configured to read data from said one-port memories in the other bank area and zero-clearing memory
areas from which data has been read, while said writing control circuit is writing data into said one bank area,
wherein the reading control circuit selects data in the one port memory in one bank area by each block to read out data, and
at a next cycle, zero-clears the read-out memory area and reads out data in an other block.
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