| US 7,549,001 B2 | ||
| Digital RAM memory circuit with an expanded command structure | ||
| Kazimierz Szczypinski, München (Germany) | ||
| Assigned to Infineon Technologies AG, Munich (Germany) | ||
| Filed on Jul. 11, 2005, as Appl. No. 11/178,915. | ||
| Claims priority of application No. 10 2004 033 387 (DE), filed on Jul. 09, 2004. | ||
| Prior Publication US 2006/0018165 A1, Jan. 26, 2006 | ||
| Int. Cl. G06F 3/00 (2006.01); G06F 13/00 (2006.01); G06F 12/00 (2006.01) | ||
| U.S. Cl. 710—71 [710/5; 711/101; 711/104; 711/105; 711/149; 711/154] | 27 Claims |
| 7. A memory device, comprising:
memory control circuitry;
a parallel interface configured to receive one or more first commands in parallel from a memory controller;
a parallel interface command decoder configured to:
receive the one or more first commands from the parallel interface;
decode the one or more first commands; and
apply the decoded one or more first commands to the memory control circuitry;
a serial interface configured to receive one or more second commands serially from the memory controller, the one or more
second commands being a sequence of serial command bits; and
a serial interface command decoder configured to:
receive the one or more sequences of serial command bits from the serial interface;
serially decode the one or more second commands; and
apply the decoded one or more second commands to the memory control circuitry.
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