| US 7,548,944 B2 | ||
| Statistics collection framework for a network processor | ||
| Ravi L. Sahita, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jul. 15, 2003, as Appl. No. 10/620,488. | ||
| Prior Publication US 2005/0013293 A1, Jan. 20, 2005 | ||
| Int. Cl. G06F 15/173 (2006.01) | ||
| U.S. Cl. 709—200 | 23 Claims |
| 1. A method of operating a network processor, the method comprising:
writing, to a shared memory accessible by multiple packet processing engines, a dynamic packet rule set, each rule specifying
a packet offset, a data pattern, and an action code;
writing, to an instruction store for the packet processing engines, execution instructions referencing the dynamic packet
rule set; and
on at least one of the packet processing engines, while processing a packet and in response to the execution instructions,
loading a first packet rule from the dynamic packet rule set, comparing packet data at the packet offset specified in the
first packet rule to the data pattern specified in the first packet rule, and, when the comparison indicates a match, performing
an action indicated by the action code specified in the first packet rule,
wherein performing the action comprises incrementing a counter specified in the first packet rule, wherein the counter is
located in a local memory area accessible by each packet processing engine, and wherein incrementing the counter comprises
blocking other processors from accessing the counter during the increment.
|