| US 7,548,447 B2 | ||
| Semiconductor memory device and methods thereof | ||
| Jin-Young Kim, Seoul (Korea, Republic of); and Ki-Whan Song, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Nov. 28, 2006, as Appl. No. 11/604,823. | ||
| Claims priority of application No. 10-2005-0125593 (KR), filed on Dec. 19, 2005. | ||
| Prior Publication US 2007/0138524 A1, Jun. 21, 2007 | ||
| Int. Cl. G11C 11/24 (2006.01); G11C 11/34 (2006.01); H01L 27/108 (2006.01) | ||
| U.S. Cl. 365—150 [365/149; 365/185.01; 257/296; 257/302] | 3 Claims |
| 1. A semiconductor memory device, comprising:
a semiconductor substrate;
first lines oriented in one direction and separately arranged on the semiconductor substrate in another direction;
floating bodies separately arranged on the first lines at a predetermined interval at locations on which memory cells are
arranged;
gates arranged adjacently to the floating bodies and respectively insulated from the floating bodies;
word lines separately arranged above the first lines in a perpendicular direction to the first lines and electrically connected
to the gates arranged in a perpendicular direction to the first lines;
drains respectively arranged on the floating bodies; and
second lines separately arranged on the drains to overlap the first lines and electrically connected to the drains oriented
in the same direction as the first lines,
wherein lines of one group among a group of the first lines and a group of the second lines are bit lines and lines of the
other group among the group of the first lines and the group of the second lines are source lines, and a voltage applied to
the source lines during a write operation is different from a voltage applied to the source lines during a read operation.
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