| US 7,548,446 B2 | ||
| Phase change memory device and associated wordline driving circuit | ||
| Hye-jin Kim, Seoul (Korea, Republic of); Du-eung Kim, Yongin-si (Korea, Republic of); Beak-hyung Cho, Hwaseong-si (Korea, Republic of); and Hyung-rok Oh, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Dec. 29, 2005, as Appl. No. 11/319,604. | ||
| Claims priority of application No. 10-2005-0023242 (KR), filed on Mar. 21, 2005. | ||
| Prior Publication US 2006/0209616 A1, Sep. 21, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/230.08; 365/230.03] | 30 Claims |
| 1. A semiconductor memory device, comprising:
n global wordlines, where n is a positive integer;
n groups of m sub-wordlines, where m is a positive integer; and,
n groups of m wordline driving circuits controlling respective voltage levels of the sub-wordlines in response to logic levels
of the global wordlines and m address signals;
wherein each of the wordline driving circuits comprises a first transistor for maintaining a corresponding sub-wordline at
a first voltage level and a second transistor for maintaining the corresponding sub-wordline at a second voltage level, wherein
second transistor includes a first terminal and a second terminal, and wherein the second terminal is connected to receive
an inverted address signal.
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