| US 7,548,444 B2 | ||
| Memory module and memory device | ||
| Yoshinori Matsui, Tokyo (Japan); Toshio Sugano, Tokyo (Japan); and Hiroaki Ikeda, Tokyo (Japan) | ||
| Assigned to Epida Memory, Inc., Tokyo (Japan) | ||
| Filed on Dec. 31, 2007, as Appl. No. 12/3,707. | ||
| Application 12/003707 is a division of application No. 11/492981, filed on Jul. 26, 2006, granted, now 7,327,590. | ||
| Application 11/492981 is a division of application No. 10/828189, filed on Apr. 21, 2004, granted, now 7,123,497. | ||
| Claims priority of application No. 2003-115834 (JP), filed on Apr. 21, 2003. | ||
| Prior Publication US 2008/0111582 A1, May 15, 2008 | ||
| Int. Cl. G11C 5/02 (2006.01) | ||
| U.S. Cl. 365—51 [365/63; 365/236; 257/686] | 6 Claims |
| 1. A memory module comprising:
an I/O chip;
a plurality of memory chips stacked on the I/O chip; and
an interposer substrate having BGA terminals,
wherein each memory chip comprises a counter circuit, wherein said I/O chip comprises a counter start value production section,
wherein said counter start value production section and a plurality of counter circuits are connected in series, and
wherein the memory chip comprises a logic circuit which executes a logic function using a laminate number of the memory chip
for a memory chip selection signal transmitted from the I/O chip in accordance with a counter output value.
|