US 7,548,086 B2
Impedance control circuit in semiconductor device and impedance control method
Tae-Hyoung Kim, Seongnam-si (Korea, Republic of); Ji-Suk Kwon, Seoul (Korea, Republic of); and Uk-Rae Cho, Suwon-si (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (Korea, Republic of)
Filed on May 04, 2006, as Appl. No. 11/417,970.
Claims priority of application No. 10-2005-0039153 (KR), filed on May 11, 2005.
Prior Publication US 2006/0261844 A1, Nov. 23, 2006
Int. Cl. H03K 17/16 (2006.01); H03K 19/003 (2006.01); H03K 5/12 (2006.01)
U.S. Cl. 326—30  [326/83; 327/170] 15 Claims
OG exemplary drawing
 
13. An impedance control method in a semiconductor device, comprising: preparing an output driver, the output driver including an impedance detector for generating a first and a second detection voltage and a mismatch compensating unit connected in parallel with a pull-down transistor array of a commonly connected pull-up and pull-down transistor array, wherein the pull-up and pull-down array includes a plurality of pull-up transistors and a plurality of pull-down transistors, wherein each of the pull-up transistors is connected in series to a different one of the pull-down transistors, wherein the pull-up transistors are connected in parallel to one another, and wherein the pull-down transistors are connected in parallel to one another; selecting a first code representing a resistance value less than a reference resistance value for generating a pull-up control code data, and selecting a second code representing a resistance value greater than the reference resistance value for generating a pull-down control code data, so that the first and second detection voltage of the impedance detector become approximated to a predetermined reference voltage value; and using the mismatch compensating unit to reduce an impedance mismatch between the resistance values wherein the mismatch compensating unit comprises one of a pull-up or pull-down transistor and a resistor, the resistor having a resistance value of twice a unit resistance of the commonly connected pull-up and pull-down transistor array such that a mismatch between pull-up and pull-down resistances of the commonly connected pull-up and pull-down transistor array is reduced by half a digital control resolution.