| US 7,547,987 B2 | ||
| EMI reduced power inverter | ||
| Makato Torigoe, West Bloomfield, Mich. (US); Liang Shao, Ann Arbor, Mich. (US); George Saikalis, West Bloomfield, Mich. (US); Hiroki Funato, Yokohama (Japan); and Takayoshi Nakamura, Ibaraki (Japan) | ||
| Assigned to Hitachi, Ltd, Tokyo (Japan) | ||
| Filed on Jun. 22, 2006, as Appl. No. 11/425,751. | ||
| Prior Publication US 2007/0296271 A1, Dec. 27, 2007 | ||
| Int. Cl. B60L 1/00 (2006.01); B60L 3/00 (2006.01); H02G 3/00 (2006.01) | ||
| U.S. Cl. 307—10.1 | 13 Claims |
| 1. A power inverter comprising:
a printed circuit board having at least one power layer with at least a first and a second section, said sections being electrically
separated from each other on said power layer and maintained at different voltages in operation,
a circuit component connected to and powered by said first section of the power layer,
a PWM switching power supply mounted in and powered by said second section of the power layer,
an electromagnetic filter electrically connected between said sections of said power layer, said filter configured to block
at least a portion of high frequency signals between said sections while enabling said sections to be maintained at the same
DC voltage level, wherein said printed circuit board comprises:
a ground layer having a first section and a second section electrically separated from each other on said ground layer,
a load circuit, functioning as control or signal conditioning, connected to said first section of the ground layer,
a PWM switching power supply module connected to said second section of the ground layer,
a second electromagnetic filter electrically connected between said sections of said ground layer, said filter configured
to block a portion of high frequency noise from said sections of the ground layer while enabling said sections to be maintained
at the same DC voltage level.
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