| US 7,547,968 B2 | ||
| Semiconductor device | ||
| Takahiro Sugimura, Tokyo (Japan); Satoshi Imasu, Tokyo (Japan); Norihiko Sugita, Tokyo (Japan); and Takafumi Betsui, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on May 17, 2006, as Appl. No. 11/434,745. | ||
| Claims priority of application No. 2005-143402 (JP), filed on May 17, 2005. | ||
| Prior Publication US 2006/0264022 A1, Nov. 23, 2006 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01) | ||
| U.S. Cl. 257—738 [257/686; 257/737; 29/740; 29/831] | 8 Claims |
| 1. A semiconductor device, comprising:
a substrate having an upper surface and a lower surface opposing the upper surface;
a first semiconductor component having a first main surface and a first back surface opposing the first main surface, and
mounted over the upper surface of the substrate via a plurality of first bumps such that the first main surface of the first
semiconductor component opposes to the upper surface of the substrate;
a second semiconductor component having a second main surface and a second back surface opposing the second main surface,
and mounted over the upper surface of the substrate via a plurality of second bumps such that the second main surface of the
second semiconductor component opposes to the upper surface of the substrate;
a first under-filling disposed between the first main surface of the first semiconductor component and the upper surface of
the substrate;
a second under-filling disposed between the second main surface of the second semiconductor component and the upper surface
of the substrate; and
a plurality of third bumps formed on the lower surface of the substrate;
wherein a height of each of the plurality of second bumps is greater than that of each of the plurality of first bumps; and
wherein a coefficient of thermal expansion of the second under-filling is greater than that of the first under-filling.
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