| US 7,547,936 B2 | ||
| Semiconductor memory devices including offset active regions | ||
| Doo-Hoon Goo, Gyeonggi-do (Korea, Republic of); Han-Ku Cho, Gyeonggi-do (Korea, Republic of); Joo-Tae Moon, Gyeonggi-do (Korea, Republic of); Sang-Gyun Woo, Gyeonggi-do (Korea, Republic of); Gi-Sung Yeo, Seoul (Korea, Republic of); and Kyoung-Yun Baek, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Oct. 06, 2005, as Appl. No. 11/246,594. | ||
| Claims priority of application No. 10-2004-0080460 (KR), filed on Oct. 08, 2004. | ||
| Prior Publication US 2006/0076599 A1, Apr. 13, 2006 | ||
| Int. Cl. H01L 271/108 (2006.01) | ||
| U.S. Cl. 257—296 [257/390; 257/506; 257/E27.084] | 19 Claims |

| 1. A semiconductor memory device comprising:
a substrate including a plurality of active regions wherein each of the plurality of active regions has a length in a direction
of a first axis and a width in a direction of a second axis, wherein the length is greater than the width, wherein the plurality
of active regions are provided in a plurality of columns of active regions in the direction of the second axis, and wherein
active regions of adjacent columns are offset in the direction of the second axis;
a field isolation layer on the substrate surrounding the active regions of the substrate;
a plurality of pairs of wordlines on the substrate wherein each pair of wordlines crosses active regions of a respective column
of active regions, wherein each pair of wordlines defines first and second source portions of each active region of the respective
column on opposite sides of the pair of wordlines and a drain portion of each active region of the column between the pair
of wordlines; and
a plurality of bit lines on the substrate, wherein each of the plurality of bitlines crosses the plurality of pairs of wordlines
and wherein each bitline is coupled to a drain portion of a respective active region of each column of active regions; and
a drain pad electrically coupled between one of the bitlines and a drain portion of a respective one of the active regions
wherein a portion of the drain pad is between the bitline and the field isolation layer in a direction perpendicular to the
substrate wherein the drain pad extends on the field isolation layer in a first direction perpendicular to the active region
on a first side of the active region further than the drain pad extends in a second direction on a second side of the active
region wherein the first and second directions are opposite directions.
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