| US 7,547,871 B2 | ||
| Photoelectric conversion device | ||
| Hiroki Hiyama, Kanagawa (Japan); Toru Koizumi, Kanagawa (Japan); Katsuhito Sakurai, Tokyo (Japan); and Masaru Fujimura, Kanagawa (Japan) | ||
| Assigned to Canon Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Aug. 17, 2005, as Appl. No. 11/205,060. | ||
| Application 11/205060 is a division of application No. 10/372286, filed on Feb. 25, 2003, granted, now 6,960,751. | ||
| Claims priority of application No. 2002-051492 (JP), filed on Feb. 27, 2002. | ||
| Prior Publication US 2005/0268960 A1, Dec. 08, 2005 | ||
| Int. Cl. H01L 27/00 (2006.01); H01L 31/00 (2006.01) | ||
| U.S. Cl. 250—208.1 [250/214.1; 348/308; 257/443] | 13 Claims |
| 1. A photoelectric conversion apparatus including a single semiconductor substrate on which are arranged a plurality of photoelectric
conversion elements, a read-out circuit unit that reads out analog signals from said plurality of photoelectric conversion
elements, a buffer circuit unit that drives a switch included in said read-out circuit unit, and a logic circuit unit that
processes a digital signal to supply a pulse to said buffer circuit unit, said apparatus comprising:
a second semiconductor area of a first conductivity type, formed in a first semiconductor area of said first conductivity
type to which a ground level for said buffer circuit unit is supplied; and
a fourth semiconductor area of said first conductivity type, formed in a third semiconductor area of said first conductivity
type to which a ground level for said logic circuit unit is supplied,
wherein said first semiconductor area and said third semiconductor area are separated from each other by a fifth semiconductor
area of a second conductivity type, and
wherein said logic circuit unit is connected to said buffer circuit unit, and said buffer circuit unit is connected to said
switch included in said read-out circuit unit.
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