| US 7,547,646 B2 | ||
| Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates | ||
| Henry Bernhardt, Dresden (Germany); Michael Stadtmüller, Dresden (Germany); Olaf Storbeck, Dresden (Germany); and Stefan Kainz, Dresden (Germany) | ||
| Assigned to Infineon Technologies AG, Neubiberg (Germany) | ||
| Filed on Oct. 28, 2004, as Appl. No. 10/974,797. | ||
| Claims priority of application No. 103 51 031 (DE), filed on Aug. 31, 2003; and application No. 10 2004 024 105 (DE), filed on May 14, 2004. | ||
| Prior Publication US 2005/0118777 A1, Jun. 02, 2005 | ||
| Int. Cl. H01L 21/31 (2006.01); H01L 21/469 (2006.01) | ||
| U.S. Cl. 438—775 [438/791] | 20 Claims |
| 1. A method of forming an integrated semiconductor circuit, comprising:
providing a semiconductor substrate that is formed from a monocrystalline semiconductor material;
subjecting the semiconductor material to thermal nitridation so as to form a stress relief layer on a process surface of the
semiconductor substrate, wherein the nitridation includes orienting the semiconductor substrate within a process chamber and
subjecting the semiconductor substrate to a heat treatment to cause oxygen to substantially diffuse out of the semiconductor
substrate at least down to a target depth defined by a lower edge of structures that are to be formed in the semiconductor
substrate, and the nitridation is carried out at least during a portion of the heat treatment;
applying a protective layer portion of a mask to the stress relief layer, wherein the protective layer portion is made from
a covering material with an expansion coefficient that is significantly different from that of the semiconductor material;
and
patterning the mask via photolithography and imaging the pattern of the mask to form a trench structure in the semiconductor
substrate.
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