| US 7,547,628 B2 | ||
| Method for manufacturing capacitor | ||
| Noriaki Ikeda, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Nov. 13, 2006, as Appl. No. 11/598,036. | ||
| Claims priority of application No. 2005-328996 (JP), filed on Nov. 14, 2005. | ||
| Prior Publication US 2007/0111434 A1, May 17, 2007 | ||
| Int. Cl. H01L 21/4763 (2006.01) | ||
| U.S. Cl. 438—637 [438/672; 438/675; 438/700; 257/E21.577; 257/E21.585] | 9 Claims |
| 1. A method for manufacturing a semiconductor device, comprising:
depositing an interlayer insulating film on or above a plug connected to a switching element;
forming a hole in said interlayer insulating film such that an opening portion of said hole is surrounded by an overhang structure
and that said plug is exposed in a bottom of said hole;
removing said overhang structure;
forming a lower electrode of a capacitor on an inner surface of said hole;
forming a dielectric on said lower electrode; and
forming an upper electrode of the capacitor on said dielectric.
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