| US 7,547,588 B2 | ||
| Thin film transistor array panel | ||
| Seung-Jae Kang, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Appl. No. 10/564,820 PCT Filed Jul. 14, 2004, PCT No. PCT/KR2004/001747 § 371(c)(1), (2), (4) Date Jan. 13, 2006, PCT Pub. No. WO2005/006069, PCT Pub. Date Jan. 20, 2005. |
||
| Claims priority of application No. 10-2003-0047756 (KR), filed on Jul. 14, 2003. | ||
| Prior Publication US 2006/0197085 A1, Sep. 07, 2006 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 21/84 (2006.01) | ||
| U.S. Cl. 438—149 [438/158; 349/141; 257/E21.414] | 9 Claims |
| 1. A thin film transistor (“TFT”) array panel comprising:
first and second gate lines transmitting gate signals to adjacent pixel electrodes and disposed adjacent to each other;
a data line insulated from the first and the second gate lines;
a first thin film transistor connected to the first gate line and the data line, and including a first drain electrode overlapping
the second gate line;
a second thin film transistor connected to the second gate line and the data line, disposed opposite the first thin film transistor
with respect to the data line, and including a second drain electrode overlapping the first gate line;
a first pixel electrode connected to the first drain electrode and overlapping the second gate line; and
a second pixel electrode connected to the second drain electrode and overlapping the first gate line.
|