	US 7,546,502 B2
	1114.9 tap linking modules
Lee D. Whetsel, Parker, Tex. (US); Baher S. Haroun, Allen, Tex. (US); Brian J. Lasher, Bellaire, Tex. (US); and Anjali Kinra, Baton Rouge, La. (US)
Assigned to Texas Instruments Incorporated, Dallas, Tex. (US)
Filed on May 08, 2008, as Appl. No. 12/117,207.
Application 12/117207 is a division of application No. 11/279503, filed on Apr. 12, 2006, granted, now 7,389,456.
Application 11/279503 is a division of application No. 09/864509, filed on May 24, 2001, granted, now 7,058,862.
Claims priority of provisional application 60/207691, filed on May 26, 2000.
Prior Publication US 2008/0215282 A1, Sep. 04, 2008
Int. Cl. G01R 31/28 (2006.01)

U.S. Cl. 714—726

7 Claims

1. An integrated circuit comprising:

A. a test clock input lead;

B. a test reset input lead;

C. a test data in input lead;

D. a test data out output lead;

E. a test mode select input lead;

F. first TAP circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, and a test mode select input;

G. second TAP circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, and a test mode select input;

H. input linking circuitry selectively coupling the test data in input lead to the test data input of the first and second TAP circuitry and selectively coupling the test mode select input lead to the test mode select input of the first and second TAP circuitry in response to input linking control signal inputs;

I. output linking circuitry selectively coupling test data outputs of the first and second TAP circuitry to the test data out output lead in response to output linking control signal inputs; and

J. TAP linking module circuitry having a test data input, a test data output, a test clock input connected to the test clock input lead, a test reset input connected to the test reset input lead, a test mode select input connected to the test mode select input lead, and input and output linking control signal outputs respectively connected to the linking control signal inputs of the input linking circuitry and the output linking circuitry, the test input and the test data output being coupled in series with the test data in input lead and the test data out output lead.