| US 7,546,498 B1 | ||
| Programmable logic devices with custom identification systems and methods | ||
| Howard Tang, San Jose, Calif. (US); Om P. Agrawal, Los Altos, Calif. (US); and Fabiano Fontana, San Jose, Calif. (US) | ||
| Assigned to Lattice Semiconductor Corporation, Hillsboro, Oreg. (US) | ||
| Filed on Jun. 02, 2006, as Appl. No. 11/446,308. | ||
| Int. Cl. G01R 31/28 (2006.01); G06F 21/00 (2006.01) | ||
| U.S. Cl. 714—724 [714/727; 713/182] | 19 Claims |
| 1. A programmable logic device comprising:
a JTAG state machine;
a JTAG instruction decoder coupled to the JTAG state machine;
a JTAG multiplexer coupled to the JTAG instruction decoder and a control circuit;
a first non-volatile memory adapted to store a first identification code of the programmable logic device;
a second memory adapted to store a second identification code of the programmable logic device; and
the control circuit adapted to select between the first identification code stored in the first non-volatile memory and the
second identification code stored in the second memory to provide as an identification code for the programmable logic device,
wherein the control circuit comprises:
a multiplexer coupled to the first non-volatile memory and the second memory; and
a third non-volatile memory adapted to control the multiplexer to provide one of the first identification code and the second
identification code as a multiplexer output signal to the JTAG multiplexer to provide as the identification code on a test
data output path.
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