| US 7,546,444 B1 | ||
| Register set used in multithreaded parallel processor architecture | ||
| Gilbert Wolrich, Framingham, Mass. (US); Matthew J. Adiletta, Worcester, Mass. (US); William R. Wheeler, Southborough, Mass. (US); Debra Bernstein, Sudbury, Mass. (US); and Donald F. Hooper, Shrewsbury, Mass. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Appl. No. 10/70,091 PCT Filed Aug. 31, 2000, PCT No. PCT/US00/23993 § 371(c)(1), (2), (4) Date Jun. 28, 2002, PCT Pub. No. WO01/16702, PCT Pub. Date Mar. 08, 2001. |
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| Claims priority of provisional application 60/151961, filed on Sep. 01, 1999. | ||
| Int. Cl. G06F 9/00 (2006.01); G06F 12/00 (2006.01) | ||
| U.S. Cl. 712—228 | 20 Claims |
| 1. A method of maintaining execution threads in a parallel multithreaded processor comprises:
accessing, by a thread executing in the multithreaded processor, a register in a register set organized into a plurality of
windows of registers, each of the plurality of windows of registers associated with a corresponding thread, each register
in the plurality of windows of registers being relatively addressable by the corresponding thread and absolutely addressable
by two or more of the threads executing on the multithreaded processor with absolutely addressable comprises providing an
exact address of the register with the exact address specified in an instruction.
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