| US 7,545,895 B2 | ||
| High performance W-CDMA slot synchronisation for initial cell search with reduced hardware | ||
| Ser Wah Oh, Johor (Malaysia); and Christopher Aldridge, Singapore (Singapore) | ||
| Assigned to STMicroelectronics Asia Pacific Pte Ltd., Singapore (Singapore) | ||
| Appl. No. 10/486,168 PCT Filed Mar. 13, 2001, PCT No. PCT/SG01/00039 § 371(c)(1), (2), (4) Date Sep. 01, 2005, PCT Pub. No. WO02/073823, PCT Pub. Date Sep. 19, 2002. |
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| Prior Publication US 2006/0056552 A1, Mar. 16, 2006 | ||
| Int. Cl. H04L 7/00 (2006.01) | ||
| U.S. Cl. 375—354 [375/145; 375/149] | 22 Claims |
| 19. A slot synchronization device, comprising:
a first finite impulse response (FIR) I-signal filter structured to receive an I signal and produce filtered I results, including
an I sign bit;
a first FIR Q-signal filter structured to receive a Q signal and produce filtered Q results, including a Q sign bit;
a second FIR I-signal filter structured to obtain the I sign bit from the first FIR I-signal filter and produce second filtered
I results;
a second FIR Q-signal filter structured to obtain the Q sign bit from the first FIR Q-signal filter and produce second filtered
Q results;
processing means for processing the second filtered I and Q results using an algorithm, thereby providing accumulated results
that are stored in a memory, wherein the processing means are structured to successively process successive second filtered
I results and successive second filtered Q results according to the algorithm, over a same location in different slots to
obtain successive accumulated results and store the successive accumulated results in the memory; and
a physical layer processor structured to search the successive accumulated results from the memory for a peak location which
corresponds to a slot boundary.
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