| US 7,545,698 B2 | ||
| Memory test mode for charge retention testing | ||
| Anwar Safvi, Rancho Murieta, Calif. (US); and Reza Jazayeri, San Jose, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 28, 2007, as Appl. No. 11/770,575. | ||
| Prior Publication US 2009/0003099 A1, Jan. 01, 2009 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—222 [365/201] | 14 Claims |
| 1. A method, comprising:
disabling an autonomous refresh mode of a dynamic random access memory circuit on a die which is adapted to autonomously refresh
the memory cells of the memory circuit at a first autonomous refresh mode rate;
enabling a test refresh mode;
refreshing said memory cells during said test refresh mode at a second test refresh mode rate which is higher than said first
autonomous refresh mode rate and is a function of the output of a timer circuit external to the die of the memory circuit;
and
testing said memory circuit wherein the results of said testing is a function of the charge retention of said memory cells.
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