| US 7,545,684 B2 | ||
| Nonvolatile semiconductor storage device and operation method thereof | ||
| Michio Nakagawa, Yokohama (Japan); and Koji Sakui, Setagaya-ku (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Appl. No. 11/815,387 PCT Filed Feb. 03, 2006, PCT No. PCT/JP2006/301834 § 371(c)(1), (2), (4) Date Aug. 02, 2007, PCT Pub. No. WO2006/082914, PCT Pub. Date Aug. 10, 2006. |
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| Claims priority of application No. 2005-027719 (JP), filed on Feb. 03, 2005. | ||
| Prior Publication US 2008/0192549 A1, Aug. 14, 2008 | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 365—189.09 [365/185.19] | 11 Claims |
| 1. A nonvolatile semiconductor memory device comprising:
a plurality of electronically reprogrammable memory cells;
a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to
said memory cell; said circuit for applying said plurality of pulse signals comprising:
a first circuit for generating a first clock having a first amplitude voltage and a second clock having a second amplitude
voltage which is higher than said first amplitude voltage;
a second circuit for generating said plurality of said pulse signals having corresponding voltages based on said first clock
or said second clock input from said first circuit respectively; and
a third circuit for stopping an input of said first clock and said second clock to said second circuit when said plurality
of pulse signals generated by said second circuit reach said corresponding voltages respectively; and
a verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals.
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