| US 7,545,624 B2 | ||
| Multilayer chip capacitor | ||
| Byoung Hwa Lee, Gyunggi-do (Korea, Republic of); Sung Kwon Wi, Seoul (Korea, Republic of); Hae Suk Chung, Seoul (Korea, Republic of); Dong Seok Park, Seoul (Korea, Republic of); Sang Soo Park, Gyunggi-do (Korea, Republic of); and Min Cheol Park, Gyunggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electro-Mechanics Co., Ltd., Gyunggi-Do (Korea, Republic of) | ||
| Filed on Sep. 21, 2007, as Appl. No. 11/902,398. | ||
| Claims priority of application No. 10-2006-0092425 (KR), filed on Sep. 22, 2006. | ||
| Prior Publication US 2008/0074826 A1, Mar. 27, 2008 | ||
| Int. Cl. H01G 4/228 (2006.01) | ||
| U.S. Cl. 361—306.3 [361/306.1; 361/303; 361/311; 361/321.1; 361/321.2] | 17 Claims |
| 1. A multilayer chip capacitor comprising:
a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second
sides and opposing third and fourth sides;
a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body;
at least one first external electrode formed on the first side; and
at least one second external electrode formed on the second side,
wherein the at least one first external electrode is not disposed at a portion of the first side onto which the at least one
second external electrode is projected, but arranged at a certain distance from the projected portion.
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