| US 7,545,426 B2 | ||
| Image pickup apparatus | ||
| Hiroki Hiyama, Zama (Japan); Toru Koizumi, Yokohama (Japan); Katsuhito Sakurai, Tokyo (Japan); Fumihiro Inui, Yokohama (Japan); Masaru Fujimura, Atsugi (Japan); Tomoko Eguchi, Atsugi (Japan); and Masanori Ogura, Atsugi (Japan) | ||
| Assigned to Canon Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Aug. 17, 2005, as Appl. No. 11/205,049. | ||
| Application 11/205049 is a division of application No. 09/791544, filed on Feb. 26, 2001, granted, now 6,965,408. | ||
| Claims priority of application No. 2000-051908 (JP), filed on Feb. 28, 2000; and application No. 2001-040167 (JP), filed on Feb. 16, 2001. | ||
| Prior Publication US 2005/0269610 A1, Dec. 08, 2005 | ||
| Int. Cl. H04N 5/335 (2006.01) | ||
| U.S. Cl. 348—308 | 10 Claims |
| 1. A scanning circuit comprising:
a shift register; and
pulse output circuits being arranged respectively on stages of said shift register for outputting a plurality of pulses based
on a pulse from the shift register, wherein each pulse output circuit includes a level conversion circuit adapted to convert
a voltage range of the pulse from the shift register, the level conversion circuit includes a punch-through current suppression
circuit adapted to suppress a punch-through current, and the plurality of pulses outputted from the pulse output circuit have
different voltage ranges, and wherein
the level conversion circuit includes a CMOS inverter, and the punch-through current suppression circuit suppresses a current
punching through the CMOS inverter.
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