| US 7,545,298 B2 | ||
| Design structure for a digital-to-analog converter using dual-gate transistors | ||
| Wagdi William Abadeer, Jericho, Vt. (US); Anthony Richard Bonaccio, Shelburne, Vt. (US); and Joseph Andrew Iadanza, Hinesburg, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 10, 2008, as Appl. No. 12/45,055. | ||
| Application 12/045055 is a continuation in part of application No. 11/846916, filed on Aug. 29, 2007. | ||
| Prior Publication US 2009/0058704 A1, Mar. 05, 2009 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03M 1/00 (2006.01) | ||
| U.S. Cl. 341—135 [330/277; 327/295] | 14 Claims |
| 1. A design structure embodied in a machine readable medium that is executable on a computer to design, manufacture, or test
an integrated circuit, the design structure comprising:
a current mirror comprising N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for
each of said N-stages, values of n being different for each of said N stages;
an output, every dual gate transistor of each stage of said N stages connected to said output;
N inputs, each input of said N inputs connected to a different and respective stage of said N stages, any particular input
of said N inputs connected to every dual gate transistor of a stage to which said particular input is connected to; and
a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of said
N stages connected to said current reference circuit.
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